1. Field of the Invention
The present invention relates generally to a semiconductor structure and process thereof, and more specifically, to a semiconductor structure and process thereof, which directly forms an epitaxial structure in a contact hole.
2. Description of the Prior Art
Epitaxy technology is often used to form semiconductor components. The functions of the epitaxy technology are that not only can a whole single-crystalline silicon layer be formed but also problems caused in semiconductor processes can be solved. In addition, the epitaxy technology may also be used to form semiconductor components having particular functions. For instance, as a silicide process is performed, a metal layer will cover a source/drain region, so that metals in the metal layer will react with the silicon below. A silicide layer is thereby formed, which is used for electrically connecting the source/drain region (usually made of silicon or silicon compounds) below with the metal plug above as well as buffering the structural difference between both, thereby reducing sheet resistance. When silicon in the source/drain region over-reacts with the metal layer or the source/drain region is too shallow, however, the source/drain region will deplete after reacting, leading to a break down in the p-n junction. Thus, an improved method is provided, which forms an epitaxial layer before the metal layer is formed on the source/drain region. For example, epitaxial silicon or epitaxial silicon compounds can be paired with the silicon substrate. This means that the epitaxial layer located between the source/drain region and the metal layer can react with the metal layer without reducing the volume of the source/drain region.
For decades, chip manufacturers have made metal-oxide-semiconductor (MOS) transistors faster by making them smaller. As the semiconductor processes advance to the very deep sub-micron era such as 65-nm node or beyond, how to increase the driving current for MOS transistors has become a critical issue. In order to improve device performance, crystal strain technology has been developed. Crystal strain technology is becoming more and more attractive as a means for getting better performance in the field of MOS transistor fabrication. Forming an epitaxial layer on a source/drain region of a semiconductor crystal alters the speed at which charges move through the crystal. Strain makes MOS transistors work better by enabling electrical charges, such as electrons, to pass more easily through the silicon lattice of the gate channel.
As the size of a semiconductor component is scaled down, the method of forming the epitaxial layer on the source/drain region described above causes some negative effects. By using a fin-shaped field-effect transistor as an example, a source/drain region is formed in a fin-shaped structure, and an epitaxial structure covers the source/drain region. The epitaxial structure enlarges the volume of the fin-shaped structure, however, leading to a reduction of space between each fin-shaped structure. Even worse, this causes each adjacent fin-shaped structure to be merged together, giving rise to a short circuit of the semiconductor component. A way of preventing this short circuit is providing enough space between each fin-shaped structure; however, this would restrict the size of the semiconductor component and prevent the desired scaling down. The problem becomes particularly significant in a static random access memory (SRAM) having dense distribution of fin-shaped structures.